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ISL6140 Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6140 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 19 page 10 FN9039.4 the requirement, and are also readily available standard values. The three resistors (R4, R5, R6) is the recommended approach for most cases. But if acceptable values can’t be found, then consider 2 separate resistor dividers (one for each pin; both from VDD to VEE). This also allows the user to adjust or trim either trip point independently. Note that the top of the resistor dividers is shown in Figure 29 as GND (Short pin). In a system where cards are plugged into a backplane (or any other case where pins are plugged into an edge connector) the user may want to take advantage of the order in which pins make contact. Typically, pins on either end of the card make contact first (although you may not know which end is first). If you combine that with designating a pin near the center as the short pin GND, and make it shorter than the rest, then it should be the last pin to make contact. The advantage of doing this: the VDD and VEE pin connections are made first. The IC is powered up, but since the top of the resistor divider is still open, both the UV and OV pins are pulled low to VEE, which will keep the gate off. This allows the IC time to get initialized, and also allows the power supply to charge up any input capacitance. By the time the resistor divider makes contact, the power supply voltage on the card is presumably stabilized, and the IC ready to respond; when the UV pin reaches the proper voltage, the IC will turn on the GATE of the FET, and starts the controlled inrush current charging. Note that this is not a requirement; if the IC gets powered at the same time as the rest of the board, it should be able to properly control the inrush current. But if finer control is needed, there are many variables involved to consider: the number of pins in the connector; the lengths of the pins; the amount of mechanical play in the pin-to-connector interface; the amount of extra time versus the shorter pin length; the amount of input capacitance versus the ability of the power supply to charge it; the manufacturing cost adder (if any) of different length pins; etc. Applications: PWRGD/PWRGD The PWRGD/PWRGD outputs are typically used to directly enable a power module, such as a DC/DC converter. The PWRGD (ISL6140) is used for modules with active low enable (L version); PWRGD (ISL6150) for those with active high enable (H version). The modules usually have a pull-up device built-in, as well as an internal clamp. If not, an external pull-up resistor may be needed, since the output is open drain. If the pin is not used, it can be left open. For both versions, the PG comparator compares the DRAIN pin to VEE (connected to the source of the FET); if the voltage drop exceeds VPG (1.7V nominal), that implies the drop across the FET is too high, and the PWRGD pin should go in-active (power-NO-GOOD). ISL6140 (L version; Figure 6): Under normal conditions (DRAIN < VPG), the Q2 DMOS will turn on, pulling PWRGD low, enabling the module. When the DRAIN is too high, the Q2 DMOS will shut off (high impedance), and the pin will be pulled high by the external module (or an optional pull-up resistor or equivalent), disabling the module. If a pull-up resistor is used, it can be connected to any supply voltage that doesn’t exceed the IC pin maximum ratings on the high end, but is high enough to give acceptable logic levels to whatever signal it is driving. An external clamp may be used to limit the range. The PWRGD can also drive an opto-coupler (such as a 4N25), as shown in Figure 7 or LED (Figure 8). In both cases, they are on (active) when power is good. Resistors R12 or R13 are chosen, based on the supply voltage, and the amount of current needed by the loads. + - VEE VPG (1.7V) PWRGD DRAIN VDD + VIN+ VIN- ON/OFF VOUT+ VOUT- CL Q2 ACTIVE ENABLE MODULE (SECTION OF) ISL6140 (L VERSION) FIGURE 6. ACTIVE LOW ENABLE MODULE LOW OPTO PWRGD + - VEE VPG PWRGD DRAIN VDD Q2 (SECTION OF) ISL6140 (L VERSION) FIGURE 7. ACTIVE LOW ENABLE OPTO-ISOLATOR (1.7V) R12 LED (GREEN) R13 + - VEE VPG PWRGD DRAIN VDD Q2 (SECTION OF) ISL6140 (L VERSION) FIGURE 8. ACTIVE LOW ENABLE WITH LED (1.7V) ISL6140, ISL6150 |
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Descripción similar - ISL6140 |
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