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74AHC595PW Datasheet(PDF) 5 Page - NXP Semiconductors |
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74AHC595PW Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 21 page 74AHC_AHCT595_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 August 2009 5 of 21 NXP Semiconductors 74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 7. Functional description [1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. Table 3. Function table[1] Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages Fig 7. Timing diagram SH CP D S ST CP MR OE Q 0 Q 1 Q 6 Q 7 Q 7S Z-state Z-state Z-state Z-state mna556 |
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