TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1

PROCESSOR SUPERVISORY CIRCUITS

SGLS143B − DECEMBER 2002 − REVISED JUNE 2008

2

POST OFFICE BOX 655303

description (continued)

divider.

The TPS3820/3/5/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become

active. The TPS3824/5 devices include a high-level output RESET. TPS3820/3/4/8 have a watchdog timer that

is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger

also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.

In applications where the input to the WDI pin may be active (transitioning high and low) when the

TPS3820/3/4/8 is asserting RESET, the TPS3820/3/4/8 does not return to a non-reset state when the input

voltage is above Vt. If the application requires that input to WDI is active when RESET is asserted, WDI must

be decoupled from the active signal. This can be accomplished by using an N-channel FET in series with the

WDI pin, with the gate of the FET connected to the RESET output as shown in Figure 1.

WDI

RESET

TPS3824

WDI External

Figure 1

The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available

in a 5-pin SOT23-5 package. The TPS382x-xxQ devices are characterized for operation over a temperature

range of −40

°C to 125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated

circuits.