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FAN4800IN Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FAN4800IN Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 20 page © 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800 Rev. 1.0.5 3 Pin Configuration Figure 2. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 IEAO PFC transconductance current error amplifier output 2 IAC PFC gain control reference input 3 ISENSE Current sense input to the PFC current limit comparator 4 VRMS Input for PFC RMS line voltage compensation 5 SS Connection point for the PWM soft-start capacitor 6 VDC PWM voltage feedback input 7 RAMP1 (RtCt) Oscillator timing node; timing set by RT, CT 8 RAMP2 (PWM RAMP) In current mode, this pin functions as the current sense input; in voltage mode, it is the PWM input from the PFC output (feed forward ramp) 9 DC ILIMIT PWM current limit comparator input 10 GND Ground 11 PWM OUT PWM driver output 12 PFC OUT PFC driver output 13 VCC Positive supply 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO PFC transconductance voltage error amplifier output 1 2 13 12 16 14 4 5 I SENSE SS V RMS I EAO V EAO V CC GND 3 I AC 15 6 7 11 10 RAMP1 9 8RAMP2 DC I LIMIT PWM OUT PFC OUT V REF V FB FAN4800 Rev.03 V DC |
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