2 / 8 page
FM1105 - Automotive Temp.
Rev. 3.0
Apr. 2009
Page 2 of 8
Block Diagram and Truth Table
INPUTS
OUTPUT
Qn
EN
CLK
Dn
H
↑
L
L
H
↑
H
H
H
H or L
X
Q0
L
X
X
Hi-Z
L
Low voltage level
H
High voltage level
X
Don’t Care
↑
CLK rising edge
Q0 Previous output state before CLK ↑
Pin Descriptions
Pin Name
I/O
Description
D0, D1
Input
Data inputs
Q0, Q1
Output
Data outputs
CLK
Input
Clock: On a rising edge of CLK, the DN inputs are transferred to the QN outputs. While
CLK is high or low, the QN outputs do not change regardless of the state of the data
inputs. See truth table.
EN
Input
Enable. This active-high input enables the device. When low, inputs are ignored and
updates to the nonvolatile cells are prevented. When high, the device operates
normally.
VDD
Supply
Power Supply (4.5V to 5.5V)
VSS
Supply
Ground
NV
State
Saver
CLK
DN
QN
EN
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