state. They are not stipulated by output voltage level.

2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state.

from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first.

as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever

occurs first.

5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high

level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level.

6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state.

No. 6624-8/9

LC35W1000BM, BTS-70U/10U

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Data retention supply voltage

2.0

3.6

V

2.0

3.6

V

–40°C to +85°C

16

Data retention supply current

–40°C to +70°C

8

µA

+25°C

0.1

Chip enable setup time

0

ns

Chip enable hold time

5

ms

Data Retention Characteristics at Ta = –40 to +85°C

Data Retention Waveforms (1) (CE1 control)

Note: * Ta = +25°C

Data retention mode

A13494

Data Retention Waveforms (2) (CE2 control)

Data retention mode

A13495