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LC74798M Datasheet(PDF) 5 Page - Sanyo Semicon Device |
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LC74798M Datasheet(HTML) 5 Page - Sanyo Semicon Device |
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5 / 32 page  No. 5833-5/32 LC74798, 74798M Continued from preceding page. Notes: (1): When the sync level = 0.8 V (2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The values in parentheses for the background high and low levels are for blue background mode. Note: The OSD timing applies when the CMOS output circuit type is used. Parameter Symbol Conditions Ratings Unit min typ max CVOUT :VDD1 = 5.0 V, (1) 1.23 (1.16) V Background color low level VRSL VDD2 = 5.0 V (2) 1.43 (1.36) V (3) 1.83 (1.76) V CVOUT :VDD1 = 5.0 V, (1) 2.37 (2.01) V Background color high level VRSH VDD2 = 5.0 V (2) 2.57 (2.21) V (3) 2.97 (2.61) V CVOUT :VDD1 = 5.0 V, (1) 1.50 V Frame level 0 VBK0 VDD2 = 5.0 V (2) 1.70 V (3) 2.10 V CVOUT :VDD1 = 5.0 V, (1) 2.08 V Frame level 1 VBK1 VDD2 = 5.0 V (2) 2.28 V (3) 2.68 V CVOUT :VDD1 = 5.0 V, (1) 2.65 V Character level VCHA VDD2 = 5.0 V (2) 2.85 V (3) 3.25 V Parameter Symbol Conditions Ratings Unit min typ max OSD write (See figure 1.) Minimum input pulse width tW (SCLK) SCLK1 200 ns tW (CS1) CS1 (The period when CS1 is high) 1 µs Data setup time tSU (CS1) CS1 200 ns tSU (SIN) SIN1 200 ns Data hold time th (CS1) CS1 2 µs th (SIN) SIN1 200 ns One word write time tword The 8-bit data write time 4.2 µs twt The RAM data write time 1 µs PDC/VPS write (For the n-channel open-drain output circuit type. See figure 2) tCKCY SCLK2 2 µs Minimum input pulse width tCKL SCLK2 1 µs tCKH SCLK2 1 µs Setup time tICK SCLK2 10 µs Output delay time tCKO DOUT 0.5 µs Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V |
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