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LC75817E Datasheet(Hoja de datos) 4 Page - Sanyo Semicon Device

No. de Pieza. LC75817E
Descripción  1/8 to 1/10 Duty Dot Matrix LCD Display Controller/Driver with Key Input Function
Descarga  43 Pages
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Fabricante  SANYO [Sanyo Semicon Device]
Página de inicio  http://www.ssdc-jp.com/eng/
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 4 page
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No. 6144-4/43
LC75817E, 75817W
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD max
VDD
–0.3 to +7.0
V
VLCD max
VLCD
–0.3 to +11.0
V
VIN1
CE, CL, DI, INH
–0.3 to +7.0
V
Input voltage
VIN2
OSCI, KI1 to KI5, TEST
–0.3 to VDD + 0.3
V
VIN3VLCD1, VLCD2, VLCD3, VLCD4
–0.3 to VLCD + 0.3
V
VOUT1
DO
–0.3 to +7.0
V
Output voltage
VOUT2
OSCO, KS1 to KS6, P1 to P4
–0.3 to VDD + 0.3
V
VOUT3VLCD0, S1 to S60, COM1 to COM10
–0.3 to VLCD + 0.3
V
IOUT1
S1 to S60
300
µA
Output current
IOUT2
COM1 to COM10
3
mA
IOUT3
KS1 to KS6
1
mA
IOUT4
P1 to P4
5
mA
Allowable power dissipation
Pd max
Ta = 85°C
200
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
VDD
VDD
4.5
6.0
V
Supply voltage
VLCD
When the display contrast adjustment circuit is used.
7.0
10.0
V
When the display contrast adjustment circuit is not used.
4.5
10.0
V
Output voltage
VLCD0VLCD0VLCD4+4.5
VLCD
V
VLCD1VLCD1
3/4 (VLCD0VLCD4)
VLCD0V
Input voltage
VLCD2VLCD2
2/4 (VLCD0VLCD4)
VLCD0V
VLCD3VLCD3
1/4 (VLCD0VLCD4)
VLCD0V
VLCD4VLCD4
0
1.5
V
VIH1
CE, CL, DI, INH
0.8 VDD
6.0
V
Input high level voltage
VIH2
OSCI
0.7 VDD
VDD
V
VIH3
KI1 to KI5
0.6 VDD
VDD
V
Input low level voltage
VIL1
CE, CL, DI, INH, KI1 to KI5
0
0.2 VDD
V
VIL2
OSCI
0
0.3 VDD
V
Recommended external resistance
ROSC
OSCI, OSCO
33
k
Recommended external capacitance
COSC
OSCI, OSCO
220
pF
Guaranteed oscillation range
fOSC
OSC
150
300
600
kHz
Data setup time
tds
CL, DI: Figure 2
160
ns
Data hold time
tdh
CL, DI: Figure 2
160
ns
CE wait time
tcp
CE, CL: Figure 2
160
ns
CE setup time
tcs
CE, CL: Figure 2
160
ns
CE hold time
tch
CE, CL: Figure 2
160
ns
High level clock pulse width
tøH
CL: Figure 2
160
ns
Low level clock pulse width
tøL
CL: Figure 2
160
ns
DO output delay time
tdc
DO, RPU = 4.7kΩ, CL = 10pF: Figure 2*1
1.5
µs
DO rise time
tdr
DO, RPU = 4.7kΩ, CL = 10pF: Figure 2*1
1.5
µs
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V
Note: *1. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL.




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