No. 5785-3/9

LC895297

[INOUT]

(1) D0 to D7, IO0 to IO15

(3) DD0 to DD15, ZDASP, ZPDIAG

(10) IOP0 to IOP7

(15) DRESP, DREQ

Note: XTAL, XTALCK, R0, VCNT0, PDO0, R1, VCNT1, PO11, PO21, BSN1, R2, VCNT2, PO12, PO22, and BSN2

The above pins are not covered by the electrical characteristics.

The 1-bit D/A converter block pins are only measured using a logic tester; no analog measurements are performed.

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Input high-level voltage

Micro-signal amplifier. Applicable pins: EFMI

3.2

V

Input low-level voltage

1.8

V

Output high-level voltage

V

EFMO and ZEFMO

Output low-level voltage

0.4

V

EFMO and ZEFMO

Input leakage current

–10

+10

µA

Output leakage current

In high-impedance mode: Applicable pins:

–10

+10

µA

EFMO and ZEFMO

EFM Input and Output Signals

External Clock Generator PLL Circuit

Figure 1 PLL Circuit

While the circuit structure is fixed, the values of the components will vary with the circuit board capacitance and other application circuit parameters.

Symbol

Currently used value

Notes

R1

7.5 k

Ω

VCO adjustment resistor

R2

10 k

Ω

Low-pass filter resistor

R3

200

Ω

Low-pass filter phase compensation resistor

C1

0.1 µF

Low-pass filter capacitor

C2

0.1 µF

VCO bias stabilization capacitor