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FAN5236 Datasheet(PDF) 10 Page - Fairchild Semiconductor

No. de pieza FAN5236
Descripción Electrónicos  Dual Mobile-Friendly DDR / Dual-Output PWM Controller
Download  19 Pages
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Fabricante Electrónico  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5236 Datasheet(HTML) 10 Page - Fairchild Semiconductor

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© 2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5236 • Rev. 1.3.2
10
Circuit Description
Overview
The FAN5236 is a multi-mode, dual-channel PWM
controller intended for graphic chipset, SDRAM, DDR
DRAM, or other low-voltage power applications in
modern notebook, desktop, and sub-notebook PCs.
The IC integrates control circuitry for two synchronous
buck converters. The output voltage of each controller
can be set in the range of 0.9V to 5.5V by an external
resistor divider.
The two synchronous buck converters can operate from
either an unregulated DC source (such as a notebook
battery), with voltage ranging from 5.0V to 24V, or from
a regulated system rail of 3.3V to 5.0V. In either mode,
the IC is biased from a +5V source. The PWM
modulators use an average-current-mode control with
input voltage feedforward for simplified feedback loop
compensation and improved line regulation. Both PWM
controllers have integrated feedback loop compensation
that reduces the external components needed.
Depending on the load level, the converters can
operate in fixed-frequency PWM Mode or in a Hysteretic
Mode. Switch-over from PWM to Hysteretic Mode
improves the converters’ efficiency at light loads and
prolongs battery run time. In Hysteretic Mode,
comparators are synchronized to the main clock, which
allows seamless transition between the modes and
reduces channel-to-channel interaction. The Hysteretic
Mode can be inhibited independently for each channel if
variable frequency operation is not desired.
The FAN5236 can be configured to operate as a
complete DDR solution. When the DDR pin is set HIGH,
the second channel provides the capability to track the
output voltage of the first channel. The PWM2 converter
is prevented from going into Hysteretic Mode if the DDR
pin is set HIGH. In DDR Mode, a buffered reference
voltage (buffered voltage of the REF2 pin), required by
DDR memory chips, is provided by the PG2 pin.
Converter Modes and Synchronization
Table 3. Converter Modes and Synchronization
Mode
VIN
VIN Pin
DDR
Pin
PWM 2 w.r.t.
PWM1
DDR1
Battery
VIN
HIGH
IN PHASE
DDR2
+5V
R to GND
HIGH
+90°
DUAL
ANY
VIN
LOW
+180°
When used as a dual converter, as shown in Figure 6,
out-of-phase operation with 180-degree phase shift
reduces input current ripple.
For “two-step” conversion (where the VTT is converted
from VDDQ as in Figure 5) used in DDR Mode, the duty
cycle of the second converter is nominally 50% and the
optimal phasing depends on VIN. The objective is to
keep noise generated from the switching transition in
one converter from influencing the "decision" to switch
in the other converter.
When VIN is from the battery, it’s typically higher than
7.5V. As shown in Figure 7, 180° operation is
undesirable because the turn-on of the VDDQ converter
occurs very near the decision point of the VTT converter.
V
DDQ
VTT
CLK
Figure 7. Noise-Susceptible 180° Phasing for DDR1
In-phase operation is optimal to reduce inter-converter
interference when VIN is higher than 5V (when VIN is
from a battery), as shown in Figure 8. Because the duty
cycle of PWM1 (generating VDDQ) is short, the switching
point occurs far away from the decision point for the VTT
regulator, whose duty cycle is nominally 50%.
V
DDQ
V
TT
CLK
Figure 8. Optimal In-Phase Operation for DDR1
When VIN ≈ 5V, 180° phase-shifted operation can be
rejected for the reasons demonstrated in Figure 7.
In-phase operation with VIN ≈ 5V is even worse, since
the switch point of either converter occurs near the
switch point of the other converter, as seen in Figure 9.
In this case, as VIN is a little higher than 5V, it tends to
cause early termination of the VTT pulse width.
Conversely, the VTT switch point can cause early
termination of the VDDQ pulse width when VIN is slightly
lower than 5V.
V
DDQ
V
TT
CLK
Figure 9.
Noise-Susceptible In-Phase Operation
for DDR2
These problems are solved by delaying the second
converter’s clock by 90°, as shown in Figure 10. In this
way, all switching transitions in one converter take place
far away from the decision points of the other converter.
V
DDQ
V
TT
CLK
Figure 10. Optimal 90° Phasing for DDR2


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