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DAC1627D1G25 Datasheet(PDF) 9 Page - NXP Semiconductors

No. de pieza DAC1627D1G25
Descripción Electrónicos  Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

DAC1627D1G25 Datasheet(HTML) 9 Page - NXP Semiconductors

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DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
9 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Ri
input resistance
D
-
100
-
Ω
Ci
input capacitance
D
-
<tbd>
-
pF
Digital inputs/outputs (pins MDSN, MDSP)
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
C-
600
-
mV
Co(L)
output load
capacitance
between GND and pin
MDSN or MDSP
D-
-
<tbd>
pF
Ci
input capacitance between GND and pin
MDSN or MDSP
D
-
<tbd>
-
pF
Ri
input resistance
D
-
100
-
Ω
Vi
input voltage
|V
gpd| < 50 mV
[3]
C
825
-
1575
mV
Vidth
input differential
threshold voltage
|V
gpd| < 50 mV
[3]
C
−100
-
+100
mV
Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N)
VIL
LOW-level input
voltage
CGND
-
0.3VDD(1V8) V
VIH
HIGH-level input
voltage
C0.7VDD(1V8) -VDD(1V8)
V
VOL
LOW-level output
voltage
pins SDO and SDIO
C
0
-
<tbd>
V
VOH
HIGH-level
output voltage
pins SDO and SDIO
C
<tbd>
-
VDD(1V8)
V
IIL
LOW-level input
current
VIL = <tbd> V
I
-
<tbd>
-
μA
IIH
HIGH-level input
current
VIH = <tbd> V
I
-
<tbd>
-
μA
Ci
input capacitance
D
-
<tbd>
-
pF
Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)
IO(fs)
full-scale output
current
controlled by the analog
GAIN registers (see Table 46
to Table 49)
D
6.19
-
31.8
mA
default value
D
-
20
-
mA
VO
output voltage
compliance range
D
<tbd>
-
VDDA(3V3)
V
VO(cm)
common-mode
output voltage
D-
2.8
-
V
Ro
output resistance
D
-
250
-
k
Ω
Co
output
capacitance
D-
3
-
pF
NDAC(mono)
DAC
monotonicity
guaranteed
D
-
<tbd>
-
bits
Table 5.
Characteristics …continued
VDDA(1V8) =1.8 V; VDDD(1V8) =1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb =+25 °C; RL =50 Ω; IO(fs) =20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 22; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
[1]
Min
Typ
Max
Unit


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