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AD9146BCPZ Datasheet(PDF) 5 Page - Analog Devices |
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AD9146BCPZ Datasheet(HTML) 5 Page - Analog Devices |
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5 / 52 page  AD9146 Rev. 0 | Page 5 of 52 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input VIN Logic High 1.2 V Input VIN Logic Low 0.6 V CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High 1.4 V Output VOUT Logic Low 0.4 V LVDS RECEIVER INPUTS1 Applies to data, DCI, and FRAME inputs Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate See Table 5 DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self-biased input, ac-coupled 1.25 V Maximum Clock Rate 1200 MHz REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLK Frequency PLL Mode 1 GHz ≤ fVCO ≤ 2.1 GHz 15.625 525 MHz SYNC Mode See the Multichip Synchronization section for conditions 0 525 MHz SERIAL PORT INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (tPWH) 12.5 ns Minimum Pulse Width Low (tPWL) 12.5 ns Setup Time, SDIO to SCLK (tDS) 2.09 ns Hold Time, SDIO to SCLK (tDH) 0.844 ns Data Valid, SDIO to SCLK (tDV) 2.904 ns Setup Time, CS to SCLK (tDCSB) 2.38 ns 1 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter Value Unit LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles Inverse Sinc 20 Cycles |
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