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AD9484BCPZ-500 Datasheet(PDF) 6 Page - Analog Devices |
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AD9484BCPZ-500 Datasheet(HTML) 6 Page - Analog Devices |
6 / 24 page AD9484 Rev. A | Page 6 of 24 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 4. Parameter Temp Min Typ Max Unit Maximum Conversion Rate Full 500 MSPS Minimum Conversion Rate Full 50 MSPS CLK+ Pulse Width High (tCH)1 Full 0.9 11 ns CLK+ Pulse Width Low (tCL)1 Full 0.9 11 ns Output (LVDS—SDR)1 Data Propagation Delay (tPD) Full 0.85 ns Rise Time (tR) (20% to 80%) 25°C 0.15 ns Fall Time (tF) (20% to 80%) 25°C 0.15 ns DCO Propagation Delay (tCPD) Full 0.6 ns Data to DCO Skew (tSKEW) Full −0.07 +0.07 ns Latency Full 15 Clock cycles Aperture Time (tA) 25°C 0.85 ns Aperture Uncertainty (Jitter, tJ) 25°C 80 fs rms 1 See . Figure 2 Timing Diagram N – 1 N N + 2 N + 3 N + 4 N + 5 N + 1 CLK+ N – 15 N – 14 N – 13 N – 12 N – 11 CLK– DCO+ DCO– Dx+ Dx– VIN+, VIN– tA tCH tCL 1/ fS tCPD tSKEW tPD Figure 2. Timing Diagram |
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