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TC1166 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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TC1166 Datasheet(HTML) 7 Page - Infineon Technologies AG |
7 / 133 page TC1165/TC1166 Summary of Features Preliminary Data Sheet 3 V1.0, 2008-04 1 Summary of Features The TC1165/TC1166 has the following features: • High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 80 MHz operation at full temperature range • Peripheral Control Processor with single cycle instruction (PCP2) –8 Kbyte Parameter Memory (PRAM) –12 Kbyte Code Memory (CMEM) • Multiple on-chip memories –56 Kbyte Local Data Memory (SRAM) –8 Kbyte Overlay Memory –16 Kbyte Scratch-Pad RAM (SPRAM) –8 Kbyte Instruction Cache (ICACHE) – 1504 Kbyte Program Flash (for instruction code and constant data) –32 Kbyte Data Flash (e.g. 4 Kbyte EEPROM emulation) –16 Kbyte Boot ROM • 8-channel DMA Controller • Fast-response interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 • High-performance on-chip bus structure – 64-bit Local Memory Bus (LMB) to Flash memory – System Peripheral Bus (SPB) for interconnections of functional units • Versatile on-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection – Two High Speed Synchronous Serial Channels (SSCs) with programmable data length and shift direction – One Micro Second Bus (MSC) interface for serial port expansion to external power devices – Two high-speed Micro Link Interfaces (MLIs) for serial inter-processor communication – One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer 1) 1) Not applicable to TC1165 |
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