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DAC34H84IZAY Datasheet(PDF) 10 Page - Texas Instruments |
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DAC34H84IZAY Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 80 page  DAC34H84 SLAS751A – MARCH 2011 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1) Logic high differential input voltage VA,B+ 200 mV threshold Logic low differential input voltage VA,B– –200 mV threshold VCOM Input Common Mode 1.0 1.2 1.6 V ZT Internal termination 85 110 135 Ω CL LVDS Input capacitance 2 pF fINTERL Interleaved LVDS data transfer rate 1250 MSPS fDATA Input data rate 625 MSPS CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% Differential voltage(2) 0.4 1.0 V DACCLKP/N Input Frequency 1250 MHz OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n x 8 x Interp) where fDACCLK / fOSTR Frequency n is any positive integer, MHz (8 x interp) fDACCLK is DACCLK frequency in MHz Duty cycle 50% Differential voltage 0.4 1.0 V CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA 0.7 x VIH High-level input voltage V IOVDD2 0.3 x VIL Low-level input voltage V IOVDD2 IIH High-level input current -40 40 µA IIL Low-level input current -40 40 µA CI CMOS Input capacitance 2 pF IOVDD2 – Iload = –100 μA V 0.2 VOH ALARM, SDO, SDIO 0.8 x Iload = –2 mA V IOVDD2 Iload = 100 μA 0.2 V VOL ALARM, SDO, SDIO Iload = 2 mA 0.5 V DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs: DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, PARITYCDP/N, double edge latching Setup time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N, ISTRP/N and SYNCP/N reset latched ts(DATA) 150 ps and PARITYCDP/N, valid to either only on rising edge of DATACLKP/N edge of DATACLKP/N Hold time, DAB[15:0]P/N, DCD[15:0]P/N, ISTRP/N, SYNCP/N ISTRP/N and SYNCP/N reset latched th(DATA) 400 ps and PARITYCDP/N valid after either only on rising edge of DATACLKP/N edge of DATACLKP/N t(ISTR_SYNC) ISTRP/N and SYNCP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns Maximum offset between t(align) DATACLKP/N and DACCLKP/N FIFO Bypass Mode only ±300 ps rising edges (1) See LVDS INPUTS section for terminology. (2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance. 10 Copyright © 2011, Texas Instruments Incorporated |
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