LIM

SENSE

25 mV

I

=

R

TPS24700

TPS24701

SLVSAL3B

– MARCH 2011 – REVISED MAY 2011

www.ti.com

DETAILED PIN DESCRIPTIONS

The following description relies on the typical application diagram shown on the front page of this data sheet, as

well as the functional block diagram of Figure 4.

EN: Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor

divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets a

TPS24700 that has latched off due to a fault condition. This pin should not be left floating.

GATE: This pin provides gate drive to the external MOSFET. A charge pump sources 30

µA to enhance the

the TPS24700/1 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold voltage.

threshold, then MOSFET M1 is turned off. The GATE pin is disabled by the following three mechanisms:

1. GATE is pulled down by an 11-mA current source when

2. GATE is pulled down by a 1-A current source for 13.5

µs when a hard output short circuit occurs and

an 11-mA sustaining current ensures that the external MOSFET remains off.

3. GATE is discharged by a 20-k

Ω resistor to GND if the chip die temperature exceeds the OTSD rising

threshold.

GATE remains low in latch mode (TPS24700) and attempts a restart periodically in retry mode (TPS24701).

If used, any capacitor connecting GATE and GND should not exceed 1

μF and it should be connected in series

with a resistor of no less than 1 k

Ω. No external resistor should be directly connected from GATE to GND or from

GATE to OUT.

GND: This pin is connected to system ground.

OUT: This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The

power-good indicator (PGb) relies on this information. The OUT pin should be protected from negative voltage

transients by a clamping diode or sufficient capacitors. A Schottky diode of 3 A / 40 V in an SMC package is

recommended as a clamping diode for high-power applications. The OUT pin should be bypassed to GND with a

low-impedance ceramic capacitor in the range of 10 nF to 1

μF.

PGb: This active-low, open-drain output is intended to interface to downstream dc/dc converters or monitoring

circuits. PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms

deglitch delay has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb assumes high-impedance

the following conditions:

•

•

threshold has been exceeded.

•

•

•

Die temperature exceeds the OTSD threshold.

this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit

(1)

6

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© 2011, Texas Instruments Incorporated

Product Folder Link(s): TPS24700 TPS24701