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TPS24720 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS24720 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 37 page LIM PROG SENSE 3125 P R R = ´ J(MAX) C(MAX) LIM θJC(MAX) T T P < R - SET LIM IMON SENSE 0.675 V R I = R R ´ ´ T FLT 10 A C = t 1.35 V ´ TPS24720 www.ti.com SLVSAL1B – MARCH 2011 – REVISED MAY 2011 • VENSD is below its threshold. • VVCC drops below the UVLO threshold. • VOV is above its rising threshold. • Die temperature exceeds the OTSD threshold. This pin can be left floating when not used. PROG: A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 k Ω. To set the maximum power, use Equation 1, (1) where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of MOSFET M1, given by Equation 2, (2) where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C. SENSE: This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is set by Equation 3. (3) A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV. SET: A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current limit and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value of RSET can be calculated from Equation 3 (see SENSE). TIMER: A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 4. (4) As is explained in the description of the LATCH pin, either latch mode or retry mode occurs if the load current exceeds the current limit threshold or the fast-trip shutdown threshold, depending on the status of the LATCH pin. While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the 16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT, can also be discharged to GND during latch mode or retry mode in the following two ways: 1. A 2-mA current sinks TIMER whenever any of the following occurs: – VEN is below its falling threshold. – VVCC drops below the UVLO threshold. – VOV is above its rising threshold. 2. A 100-k Ω resistor is connected to TIMER and discharges CT at the moment when VENSD drops below its threshold. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS24720 |
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