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ISLA214P50 Datasheet(PDF) 1 Page - Intersil Corporation

No. de pieza ISLA214P50
Descripción Electrónicos  12-Bit, 500MSPS ADC Programmable Built-in Test Patterns
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Fabricante Electrónico  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA214P50 Datasheet(HTML) 1 Page - Intersil Corporation

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12-Bit, 500MSPS ADC
ISLA212P50
The ISLA212P50 is a 12-bit, 500MSPS analog-to-digital converter
designed with Intersil’s proprietary FemtoCharge™ technology on
a standard CMOS process. The ISLA212P50 is part of a
pin-compatible portfolio of 12 to 16-bit A/Ds with maximum
sample rates ranging from 130MSPS to 500MSPS.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single 500MHz
conversion clock is presented to the converter, and all interleave
clocking is managed internally. The proprietary Intersil Interleave
Engine (I2E) performs automatic correction of offset, gain, and
sample time mismatches between the unit ADCs to optimize
performance.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue offline and
continuous calibration commands as well as configure many
dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA212P50 is available in a 72 Ld QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 500MSPS
= 70.3dBFS fIN = 30MHz
= 68.7dBFS fIN = 363MHz
• SFDR @ 500MSPS
= 84dBc fIN = 30MHz
= 76dBc fIN = 363MHz
• Total Power Consumption = 823mW @ 500MSPS
Features
• Automatic Fine Interleave Correction Calibration
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
•Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
DIGITAL
ERROR
CORRECTION
SHA
VINP
VINN
12-BIT
250 MSPS
ADC
CLOCK
MANAGEMENT
SHA
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
VREF
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
+
VCM
VREF
I2E
Gain, Offset
and Skew
Adjustments
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
ISLA216P20
16
200
ISLA216P13
16
130
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
May 25, 2011
FN7843.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.


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