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ISL28005FH100Z-T7A Datasheet(PDF) 9 Page - Intersil Corporation

No. de pieza ISL28005FH100Z-T7A
Descripción Electrónicos  Micropower, Rail-to-Rail Input Current Sense Amplifier
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Fabricante Electrónico  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL28005FH100Z-T7A Datasheet(HTML) 9 Page - Intersil Corporation

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ISL28005
9
FN6973.4
July 1, 2011
Applications Information
Functional Description
The ISL28005-20, ISL28005-50 and ISL28005-100 are single
supply, uni-directional current sense amplifiers with fixed gains
of 20V/V, 50V/V and 100V/V respectively.
The ISL28005 is a 2-stage amplifier. Figure 18 shows the active
circuitry for high-side current sense applications where the sense
voltage is between 1.35V to 28V. Figure 19 shows the active
circuitry for ground sense applications where the sense voltage is
between 0V to 1.35V.
The first stage is a bi-level trans-conductance amp and level
translator. The gm stage converts the low voltage drop (VSENSE)
sensed across an external milli-ohm sense resistor, to a current
(@ gm = 21.3µA/V). The trans-conductance amplifier forces a
current through R1 resulting to a voltage drop across R1 that is
equal to the sense voltage (VSENSE). The current through R1 is
mirrored across R5 creating a ground-referenced voltage at the
input of the second amplifier equal to VSENSE.
The second stage is responsible for the overall gain and
frequency response performance of the device. The fixed gains
(20, 50, 100) are set with internal resistors Rf and Rg. The only
external component needed is a current sense resistor (typically
0.001
Ω to 0.01Ω, 1W to 2W).
The transfer function is given in Equation 1.
The input gm stage derives its ~2.86µA supply current from the
input source through the RS+ terminal as long as the sensed
voltage at the RS+ pin is >1.35V and the gmHI amplifier is
selected. When the sense voltage at RS+ drops below the 1.35V
threshold, the gmLO amplifier kicks in and the gmLO output
current reverses, flowing out of the RS- pin.
Test Circuits and Waveforms
FIGURE 13. IS, VOS, VOA, CMRR, PSRR, GAIN ACCURACY
FIGURE 14. INPUT BIAS CURRENT, LEAKAGE CURRENT
FIGURE 15. SLEW RATE, ts, SATURATION RECOVERY TIME
FIGURE 16. GAIN vs FREQUENCY
FIGURE 17. SLEW RATE
RS+
VCC
RS-
VOUT
OUT
RL
GND
VSENSE
VRS+
1M
Ω
+
-
+
-
RS+
VCC
RS-
VOUT
OUT
RL
GND
VSENSE
VRS+
1M
Ω
+
-
+
-
R1
R2
VR1
VR2
RS+
VCC
RS-
VOUT
OUT
RL
GND
VRS-
VRS+
1M
Ω
PULSE
GENERATOR
RS+
VCC
RS-
VOUT
OUT
RL
GND
VSENSE
VRS+
1M
Ω
SIGNAL
GENERATOR
RS+
VCC
RS-
VOUT
OUT
RL
GND
VRS+
1M
Ω
PULSE
GENERATOR
VOUT
GAIN
ISRS VOS
+
()
×
=
(EQ. 1)


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