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ISL31483EIBZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL31483EIBZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 24 page ISL31480E, ISL31483E, ISL31485E, ISL31486E 3 FN7638.2 Pin Configurations ISL31483E (14 LD SOIC) TOP VIEW ISL31485E (8 LD SOIC) TOP VIEW RINV RO RE DE DI GND GND VCC VCC A B Z Y DINV 1 2 3 4 5 6 7 14 13 12 11 10 9 8 D R RO INV DE DI 1 2 3 4 8 7 6 5 VCC B/Z A/Y GND D R Pin Descriptions PIN NAME ISL31480E PIN # ISL31483E PIN # ISL31485E PIN # ISL31486E (12 LD) PIN # ISL31486E (10 LD) PIN # ISL31486E (14 LD) PIN # FUNCTION RO 2 211 11 Receiver output. On the ISL31480E, or if INV or RINV is low, then: If A - B ≥ -10mV, RO is high; if A - B ≤ -200mV, RO is low. If INV or RINV is high, then: If B - A ≥ -10mV, RO is high; if B - A ≤ -200mV, RO is low. In all cases, RO = High if A and B are unconnected (floating), or shorted together, or connected to an undriven, terminated bus (i.e., Rx is always failsafe open, shorted, and idle, even if polarity is inverted). RE 4 3 N/A 2 2 2 Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. Internally pulled low. DE 3 4 3 4 4 4 Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high, and they are high impedance when DE is low. Internally pulled high (to VL on ISL31480E and ISL31486E; to VCC on other versions). DI 5 5 4 5 5 6 Driver input. On the ISL31480E, or if INV or DINV is low, a low on DI forces output Y low and output Z high, while a high on DI forces output Y high and output Z low. The output states relative to DI invert if INV or DINV is high. GND 6 6, 7 5 7, 8 6 8, 9 Ground connection.This is also the potential of the TDFN EPAD. A/Y 8 N/A 6 9 7 11 ±60V Fault Protected RS-485/RS-422 level I/O pin. On the ISL31480E, or if INV is low, A/Y is the non-inverting receiver input and non-inverting driver output. If INV is high, A/Y is the inverting receiver input and the inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. |
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