Technical Note

3/16

BU9829GUL-W

www.rohm.com

2010.09 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

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Synchronous data input/output timing

SI data is latched into the chip at the rising edge of SCK clock.

Address and data must be transferred from MSB.

SO data toggles at the falling edge of SCK clock.

Output data toggles from MSB.

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AC condition

●

Pin configuration

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Pin function

Land

No.

Pin

Name

I/O

Function

A1

Vcc1

－

Power Supply (EEPROM)

A2

CSB

IN

Chip Select Control

A3

SCK

IN

Serial Data Clock Input

B1

Vcc2

－

Power Supply (LDO)

B2

SI

IN

Start Bit, Op.code, Address, Serial Data Input

B3

SO

OUT Serial Data Output

C1

OUT LDO Regulator Output

C2

GND

－

Ground (0V)

C3

LDOEN

IN

LDO Regulator Enable

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LDO regulator DC operating characteristics (Unless otherwise specified Ta=-30～85℃)

Parameter

Symbol

Specification

Unit

test condition

Min.

Typ.

Max.

2.9

3.0

3.2

V

3.2V≦Vcc2≦3.6V, IOUT=0, 2mA, VSET=1, 0=[1:1]

2.9

3.0

3.1

V

3.2V≦Vcc2≦3.6V, IOUT=2, 10mA, VSET=1, 0=[1:1]

2.8

2.9

3.1

V

3.1V≦Vcc2≦3.6V, IOUT=0, 2mA, VSET=1, 0=[1:0]

2.8

2.9

3.0

V

3.1V≦Vcc2≦3.6V, IOUT=2, 10mA, VSET=1, 0=[1:0]

2.7

2.8

3.0

V

3.0V≦Vcc2≦3.6V, IOUT=0, 2mA, VSET=1, 0=[0:1]

2.7

2.8

2.9

V

3.0V≦Vcc2≦3.6V, IOUT=2, 10mA, VSET=1, 0=[0:1]

2.6

2.7

2.9

V

2.9V≦Vcc2≦3.6V, IOUT=0, 2mA, VSET=1, 0=[0:0]

2.6

2.7

2.8

V

2.9V≦Vcc2≦3.6V, IOUT=2, 10mA, VSET=1, 0=[0:0]

Operating Current

-

-

200

µA

Vcc2=3.6V, IOUT=0A

Standby Current

-

-

1.0

µA

Vcc2=3.6V, IOUT=0A, LDOEN=GND

“H” Input Voltage

VIH

1.4

-

Vcc2+0.3

V

2.9V≦Vcc2≦3.6V

“L” Input Voltage

VIL

-0.3

-

0.6

V

2.9V≦Vcc2≦3.6V

○

This product is not designed for protection against radioactive rays.

Parameter

Symbol

Limits

Unit

Min.

Typ.

Max.

Load Capacitance

CL

-

-

100

pF

Input Rise times

-

-

-

50

ns

Input Fall times

-

-

-

50

ns

Input Pulse Voltage

-

0.25Vcc1/0.75Vcc1

V

Input and Output Timing Reference Voltages

-

0.3VCc1/0.7Vcc1

V

Fig.1 Input timing

Fig.2 Input and output timing

1

2

3

C

B

A

C1

B1

A1

C2

B2

A2

INDEX POST

C3

B3

A3

Fig.3 Pin configuration (bottom view)

SO

SI

Hi-Z

CSB

SCK

tON

tCSS

tSCKS

tSCKWL

tSCKWH

tDIS

tDIH

tRC

tFC

VCC1

CSB

SCK

SO

SI

tCS

tSCKH

tCSH

Hi-Z

tOH

tOZ

tPD

tRO,tFO