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BU9833GUL-W Datasheet(PDF) 3 Page - Rohm |
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BU9833GUL-W Datasheet(HTML) 3 Page - Rohm |
3 / 19 page Technical Note 3/18 www.rohm.com 2010.10 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. BU9833GUL-W ● Action timing Characteristics (Unless otherwise specified, Ta=-40~+85℃,Vcc=1.7~5.5V) Parameter Symbol FAST-MODE 2.5V≦Vcc≦5.5V STANDARD-MODE 2.5V≦Vcc≦5.5V Unit Min. Typ. Max. Min. Typ. Max. SCL frequency fSCL - - 400 - - 100 kHz Data clock “HIGH” time tHIGH 0.6 - - 4.0 - - μs Data clock “LOW” time tLOW 1.2 - - 4.7 - - μs SDA, SCL rise time *1 tR *1 - - 0.3 - - 1.0 μs SDA< SCL fall time *1 tF *1 - - 0.3 - - 0.3 μs Start condition hold time tHD:STA 0.6 - - 4.0 - - μs Start condition setup time tSU:STA 0.6 - - 4.7 - - μs Input data hold time tHD:DAT 0 - - 0 - - ns Input data setup time tSU:DAT 100 - - 250 - - ns Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs Output data hold time tDH 0.1 - - 0.2 - - μs Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs Internal write cycle time tWR - - 5 - - 5 ms Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs WP hold time tHD:WP 0 - - 0 - - ns WP setup time tSU:WP 0.1 - - 0.1 - - μs WP valid time tHIGH:WP 1.0 - - 1.0 - - μs *1 Not 100% tested. ● Sync data input / output timing SCL SDA WP tHD:WP tWR D1 D0 ACK ACK DATA(1) DATA(n) tSU:WP stop condition ○ Input read at the rise edge of SCL ○ Data output in sync with the fall of SCL Fig.-1(a) Sync data input / output timing Fig.1-(b) Start – stop bit timing fig.1-(d) WP timing at write execution Fig.1-(e) WP timing at write cancel ○ At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP=“LOW” ○ By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Fig.1-(c) Write cycle timing SDA (Input) SCL SDA (Output) tHD:STA tHD:DAT tSU:DAT tBUF tPD tDH tLOW tHIGH tR tF SDA D0 ACK tWR SCL Write data (n-th address) Stop condition Start condition tHIGH:WP WP SDA D1 D0 ACK ACK DATA(1) DATA(n) tWR SCL SDA tSU:STA tSU:STO tHD:STA START BIT STOP BIT SCL |
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