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74AUP1G07GW Datasheet(PDF) 2 Page - NXP Semiconductors |
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74AUP1G07GW Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 18 page 74AUP1G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 2 September 2010 2 of 18 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output 3. Ordering information 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G07GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G07GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74AUP1G07GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 74AUP1G07GN −40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm SOT1115 74AUP1G07GS −40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 Table 2. Marking Type number Marking code[1] 74AUP1G07GW pS 74AUP1G07GM pS 74AUP1G07GF pS 74AUP1G07GN pS 74AUP1G07GS pS Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna623 AY 2 4 mna624 4 2 A Y mna625 A Y GND |
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