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DAC1408D650 Datasheet(PDF) 7 Page - NXP Semiconductors |
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DAC1408D650 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 98 page DAC1408D650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 26 November 2010 7 of 98 NXP Semiconductors DAC1408D650 2 , 4 or 8 interpolating DAC with JESD204A 9. Characteristics Table 5. Characteristics VDDA(1V8) =VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = 40 C to +85 C; typical values measured at V DDA(1V8) =VDDD =1.8 V; VDDA(3V3) =3.3 V; Tamb =+25 C; RL =50 ; IO(fs) =20mA; maximum sample rate; PLL off unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit VDDA(3V3) analog supply voltage (3.3 V) I 3.13 3.3 3.47 V VDDD(1V8) digital supply voltage (1.8 V) I 1.7 1.8 1.9 V VDDA(1V8) analog supply voltage (1.8 V) I 1.7 1.8 1.9 V IDDA(3V3) analog supply current (3.3 V) fo =19MHz; fs = 640 Msps; 4 interpolation; NCO on I- 42 - mA IDDD(1V8) digital supply current, (1.8 V) fo =19MHz; fs = 640 Msps; 4 interpolation; NCO on I - 354 - mA IDDA(1V8) analog supply current, (1.8 V) fo =19MHz; fs = 640 Msps; 4 interpolation; NCO on I - 412 - mA I DDD digital supply current difference x/sin x function on; fs =640 Msps I- 52 - mA Ptot total power dissipation fs =640 Msps; 4 interpolation; NCO off; DAC Q off C - 0.82 - W fs =640 Msps; 4 interpolation; NCO off C - 1.26 - W fs =640 Msps; 4 interpolation; NCO on C - 1.51 - W fs =625 Msps; 2 interpolation; NCO off C- 1.33 - W fs =625 Msps; 2 interpolation; NCO on C- 1.51 - W Power-down mode; fo =19MHz; fs =640 Msps; 4 interpolation; NCO on complete device; Power-down mode I- 0.04 - W DAC A and DAC B; Power-down mode I - 0.62 - W DAC A and DAC B; Sleep mode I - 0.83 - W Timing specifications td(startup) start-up delay time from full Power-down mode - 20 - ms td(restart) restart delay time from Sleep mode - 300 - ns tlock lock time maximum input rate [2] -11 - s Clock inputs (CLKINN, CLKINP)[3] Vi input voltage range: CLK+ or CLK V gpd <50mV [4] C 825 - 1575 mV |
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