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TPS40400RHLT Datasheet(PDF) 5 Page - Texas Instruments |
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TPS40400RHLT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 72 page TPS40400 www.ti.com SLUS930B – APRIL 2011 – REVISED OCTOBER 2011 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for –40°C ≤ TJ ≤ 125°C, VDD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS (VBOOT – VSW) = 6.4 V, IHDRV = –100 , RHDHI High-side driver pull up resistance 1.25 2.5 TJ = 25°C (VBOOT – VSW) = 6.4 V, IHDRV = 100 mA, RHDLO High-side driver pull down resistance 1.3 2.6 Ω TJ = 25°C RLDHI Low-side driver pull up resistance TJ = 25°C 1.25 2.5 RLDLO Low-side driver pull down resistance TJ = 25°C 0.8 1.5 tHRISE High-side driver rise time (6) 6 12.1 tHFALL High-side driver fall time (6) 6.3 12.6 CLOAD = 2.2 nF ns tLRISE Low-side driver rise time (6) 6 12.1 tLFALL Low-side driver fall time (6) 4 8 MFR_SPECIFIC_00 bit 0 = 0, tDT Anti-cross conduction time 20 50 ns (short dead time.) ISW SW pin leakage current (out of pin) VSW = 0 V 1 μA BOOTSTRAP VBOOT Internal diode voltage drop IBOOT = 5 mA 0.7 1 V IBOOT(lk) BOOT diode leakage current(6) (VBOOT – VSW) = 6 V 1 μA UVLO VDD UVLO turn on threshold(7) Factory default settings (minimum) 2.475 2.750 3.025 VUVLO(on) V 2.25 V ≤ VVDD ≤ 20 V, Accuracy(7) –10% 10% 2.75 V ≤ VIN_ON ≤ 18 V VDD UVLO turn off threshold(7) Factory default settings (minimum) 2.25 2.5 2.75 VUVLO(off) V 2.25 V < VVDD < 20 V, Accuracy(7) –10% 10% 2.75 V < VIN_OFF < 17.6 V REMOTE VOLTAGE SENSE AMPLIFIER VIOFST Input offset voltage –10 10 mV RGAIN Gain setting resistor(6) 48 60 72 k Ω VVDD > 6.5 V 0 6 VDIFFO Output voltage at DIFFO pin VVDD = 5 V 0 4.5 V VVDD = 3 V 0 2.5 KDIFF Differential gain of amplifier 0.995 1.000 1.005 V/V VAGBWP Closed loop bandwidth(6) 2 MHz IVAOP Output source current VSNS+ = VDIFFO = 5 V, VSNS– = 0 V 1 mA IVAOM Output sink current VSNS+ = 0 V, VSNS– = 4.5 V, VDIFFO = 5 V 1 mA POWERGOOD FB pin voltage upper limit for power good on 648 Factory default settings mV VPGON FB pin voltage lower limit for power good on 552 Accuracy 540 mV < VPGON < 660 mV –5% 5% FB pin voltage upper limit for power good off 660 mV Factory default settings VPGOFF FB pin voltage lower limit for power good off 540 Accuracy 528 mV < VPGOFF < 672 mV –5% 5% RPGD Pull down resistance of PGD pin VFB = 0, IPGOOD = 5 mA 50 Ω Factory default settings , IPGDLK Leakage current 3 15 μA 550 mV < VFB < 650 mV, VPGOOD = 5 V tPGD Delay filter from FB(6) 5 μs (6) Ensured by design. Not production tested. (7) Although specifications appear to overlap, hysteresis is assured for UVLO turn on and turn off thresholds. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s) :TPS40400 |
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