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LC8784C8PB Datasheet(PDF) 10 Page - Sanyo Semicon Device |
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LC8784C8PB Datasheet(HTML) 10 Page - Sanyo Semicon Device |
10 / 29 page LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB No.A1795-10/29 Serial I/O Characteristics at Ta = -40 °C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pins/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 tSCKH(1) • See Fig. 2. 1 tSCKHA(1a) • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. • See Fig. 2. • (Note 4-1-2) 4 High level pulse width tSCKHA(1b) SCK0(P12) • Continuous data transmission/reception mode • SIO2 is in use simultaneous. • See Fig. 2. • (Note 4-1-2) 3.0 to 5.5 6 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) 1/2 tSCKH(2) • CMOS output selected. • See Fig. 2. 1/2 tSCK tSCKHA(2a) • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. • CMOS output selected. • See Fig. 2. tSCKH(2) +2tCYC tSCKH(2) +(10/3)tCYC High level pulse width tSCKHA(2b) SCK0(P12) • Continuous data transmission/reception mode • SIO2 is in use simultaneous. • CMOS output selected. • See Fig. 2. 3.0 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(16/3)tCYC tCYC Data setup time tsDI(1) 0.03 Data hold time thDI(1) SI0(P11), SB0(P11) • Must be specified with respect to rising edge of SIOCLK • See fig. 2. 3.0 to 5.5 0.03 tdD0(1) • Continuous data transmission/reception mode • (Note 4-1-3) (1/3)tCYC +0.05 tdD0(2) • Synchronous 8-bit mode. • (Note 4-1-3) 1tCYC +0.05 Output delay time tdD0(3) SI0(P11), SB0(P11) • (Note 4-1-3) 3.0 to 5.5 (1/3)tCYC +0.05 μs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 2. |
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