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AM1806 Datasheet(PDF) 7 Page - Texas Instruments |
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AM1806 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 244 page  AM1806 www.ti.com SPRS658C – FEBRUARY 2010 – REVISED APRIL 2011 Revision History (continued) See ADDITIONS/MODIFICATIONS/DELETIONS Section 5.10.5, EMIFA Electrical Data/Timing: • Corrected 1.3V, 1.2V MIN value in Table 5-21. External Memory Interface A • Updated EMA_A[12:0] to EMA_A[22:0] in Figure 5-12 through Figure 5-15. (EMIFA) • Removed unused parameters 29 and 30 from Figure 5-12. • Removed unused parameters 31 and 32 from Figure 5-13. Section 5.11.1, DDR2/mDDR Memory Controller Electrical Data/Timing • Corrected 1.3V and 1.2 V MAX values in Table 5-23. Section 5.11.3.8, Net Classes: Section 5.11 DDR2/mDDR Controller • Corrected Table 5-32 column heading. Section 5.11.3.11, DDR2/mDDR CK and ADDR_CTRL Routing: • Updated Table 5-35. Section 5.16.2.1, Serial Peripheral Interface (SPI) Timing: • Added tih(SPC_SOMI)M to Table 5-61. Section 5.16.2 • Corrected MAX values and updated table note in Table 5-62. SPI Electrical Data/Timing • Updated table note in Table 5-69 • Corrected MAX values and changed table note in Table 5-70. Section 5.19 • Added Important Notice. Universal Serial Bus OTG Section 5.19.2, USB0 [USB2.0] Electrical Data/Timing: Controller (USB0) [USB2.0 OTG] • Added first paragraph. • Added 2nd paragraph. Section 5.20.1, LCD Interface Display Driver (LIDD Mode): • Removed table note for Table 5-86. Section 5.20 • Updated description for parameters 12 and 13 in Table 5-87. LCD Controller (LCDC) Section 5.20.2, LCD Raster Mode: • Updated Figure 5-53. • Extended time line in Figure 5-54. Section 5.25 Table 5-103, eHRPWM Module Control and Status Registers Grouped by Submodule: Enhanced High-Resolution Pulse-Width Modulator • Updated offset addresses for HRCNFG. (eHRPWM) Table 5-109, Timing Requirements for Timer Input: Section 5.26.1 Timer Electrical Data/Timing • Updated table note. Figure 5-75, Clock Source Section 5.27.1 Clock Source • Replaced Real Time Clock with RTC Power Source. Section 5.30 • Added Section 5.30.4, IEEE 1149.1 JTAG. Emulation Logic • Added Section 5.30.5, JTAG 1149.1 Boundary Scan Considerations. Section 6.1.2, Device Nomenclature: Section 6.1 Device Support • Updated Figure 6-1. Copyright © 2010–2011, Texas Instruments Incorporated Contents 7 Submit Documentation Feedback Product Folder Link(s): AM1806 |
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