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AD5696R Datasheet(PDF) 8 Page - Analog Devices |
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AD5696R Datasheet(HTML) 8 Page - Analog Devices |
8 / 32 page AD5696R/AD5695R/AD5694R Data Sheet Rev. 0 | Page 8 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. 16-Lead LFCSP Pin Configuration Figure 4. 16-Lead TSSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description LFCSP TSSOP 1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 7 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 8 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this pin is tied to VDD, all four DACs output a span of 0 V to 2 × VREF. 9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. 10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address. 11 13 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. 12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. 14 16 RSTSEL Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VDD powers up all four DACs to midscale. 15 1 VREF Reference Voltage. The AD5696R/AD5695R/AD5694R have a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. 16 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. 12 11 10 1 3 4 A1 SCL A0 9 VLOGIC VOUTA VDD 2 GND VOUTC AD5696R/AD5695R/AD5694R NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 VOUTB VOUTA GND VOUTD VOUTC VDD VREF SDA 16 15 14 13 12 11 10 9 RESET A1 SCL GAIN LDAC VLOGIC A0 RSTSEL TOP VIEW (Not to Scale) AD5696R/ AD5695R/ AD5694R |
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