 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD9577 Datasheet(PDF) 1 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD9577 Datasheet(HTML) 1 Page - Analog Devices |
|
|
1 / 44 page  Clock Generator with Dual PLLs, Spread Spectrum, and Margining Data Sheet AD9577 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. FEATURES Fully integrated dual PLL/VCO cores 1 integer-N and 1 fractional-N PLL Continuous frequency coverage from 11.2 MHz to 200 MHz Most frequencies from 200 MHz to 637.5 MHz available PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical PLL2 phase jitter (12 kHz to 20 MHz) Integer-N mode: 470 fs rms typical Fractional-N mode: 660 fs rms typical Input crystal or reference clock frequency Optional reference frequency divide-by-2 I2C programmable output frequencies Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks 1 CMOS buffered reference clock output Spread spectrum: downspread [0, −0.5]% 2 pin-controlled frequency maps: margining Integrated loop filters Space saving, 6 mm × 6 mm, 40-lead LFCSP package 1.02 W power dissipation (LVDS operation) 1.235 W power dissipation (LVPECL operation) 3.3 V operation APPLICATIONS Low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital video Spread spectrum clocking GENERAL DESCRIPTION The AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I2C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining. Other applications with demanding phase noise and jitter requirements can benefit from this part. The first integer-N PLL section (PLL1) consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), a programmable FUNCTIONAL BLOCK DIAGRAM XTAL OSC REFCLK XT1 XT2 MARGIN REFSEL CMOS AD9577 DIVIDE 1 OR 2 VCO 2.15GHz TO 2.55GHz LDO FEEDBACK DIVIDER LVPECL/LVDS REFOUT OR 2 × CMOS LVPECL/LVDS OR 2 × CMOS PLL1 VCO 2.15GHz TO 2.55GHz LDO FEEDBACK DIVIDER LVPECL/LVDS OR 2 × CMOS LVPECL/LVDS OR 2 × CMOS PLL2 SCL SDA I2C CONTROL SSCG MAX_BW SPREAD SPECTRUM, SDM Figure 1. feedback divider, and two independently programmable output dividers. By connecting an external crystal or applying a reference clock to the REFCLK pin, frequencies of up to 637.5 MHz can be synchronized to the input reference. Each output divider and feedback divider ratio is I2C programmed for the required output rates. A second fractional-N PLL (PLL2) with a programmable modulus allows VCO frequencies that are fractional multiples of the reference frequency to be synthesized. Each output divider and feedback divider ratio can be programmed for the required output rates, up to 637.5 MHz. This fractional-N PLL can also operate in integer-N mode for the lowest jitter. Up to four differential output clock signals can be configured as either LVPECL or LVDS signaling formats. Alternatively, the outputs can be configured for up to eight CMOS outputs. Combinations of these formats are supported. No external loop filter components are required, thus conserving valuable design time and board space. The AD9577 is available in a 40-lead, 6 mm × 6 mm LFCSP package and can operate from a single 3.3 V supply. The operating temperature range is −40°C to +85°C. |
Número de pieza similar - AD9577 |
|
Descripción similar - AD9577 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
