ADXL362 datasheet(9/40 Pages) AD

No. de pieza	ADXL362

Descripción Electrónicos	Micropower Three-Axis 짹2g/짹4g/짹8g

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Fabricante Electrónico	AD [Analog Devices]

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Preliminary Technical Data

ADXL362

Rev. PrB | Page 9 of 40

Table 6. Noise and current consumption in normal

operation, Low Noise Mode, and Ultra-Low Noise Mode @ VS

= 2.0 V

Mode

Noise

[µg/√Hz]

(Typical)

Current

Consumption

[µA] (Typical)

Normal

Operation

550

1.8

Low Noise

400

3.0

Ultra-Low

Noise

250

10

Table 7. Noise and current consumption in normal

operation, Low Noise Mode, and Ultra-Low Noise Mode @ VS

= 3.3 V

Mode

Noise

[µg/√Hz]

(Typical)

Current

Consumption

[µA] (Typical)

Normal

Operation

380

2.7

Low Noise

280

4.5

Ultra-Low

Noise

175

15

Anti-Aliasing

The ADXL362’s analog-to-digital converter (ADC) samples at

the (user-selected) output data rate. In the absence of anti-

aliasing filtering, it would therefore alias any input signals

whose frequency is more than half the data rate. To mitigate

this, a two-pole low-pass filter is provided at the input of the

ADC. This anti-aliasing filter can be set by the user to have a

bandwidth of one-half the data rate or one-fourth the data rate.

Setting the anti-aliasing filter pole to ½ the output data rate

provides less aggressive anti-aliasing filtering, but maximizes

bandwidth and is adequate for most applications. Setting the

pole to ¼ the data rate reduces bandwidth for a given data rate,

but provides more aggressive anti-aliasing.

The ADXL362’s anti-aliasing filter defaults to the more

conservative setting, where bandwidth is set to ¼ the output

data rate.

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