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TPS51601ADRBR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS51601ADRBR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page TPS51601A SLUSAP3 – MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VVDD = 5.0 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY, UNDERVOLTAGE LOCKOUT PWM = HI 160 220 IVDD VDD bias current PWM = LO 500 µA PWM = float 50 VUVLO(h) VDD UVLO ‘OK’ threshold 3.5 3.7 3.9 V VUVLO(l) VDD UVLO fault threshold 3.3 3.5 3.7 V VUVLO(hys) VDD UVLO hysteresis 0.2 V PWM INPUT VIH(pwm) HIGH-level PWM input 4.0 V VIL(pwm) LOW-level PWM input 0.7 V RVDD-PWM VDD-to-PWM resistance 30 k Ω RPWM-GND PWM-to-GND resistance 20 k Ω VPWM(tri) PWM tri-state voltage PWM floating 1.5 2.5 V SKIP INPUT VIH(skip) HIGH-level SKIP input logic 2.2 V VIL(skip) LOW-level SKIP input logic 0.7 V ILSKIP-GND SKIP-to-GND leakage VSKIP = 5 V 2 µA GATE DRIVE OUTPUT Source resistance, (VBST –VLL) = 5 V, 1.0 2.5 HIGH-state (VBST – VDRVH) = 0.1 V RDRVH DRVH on resistance Ω Sink resistance, (VBST –VLL) = 5 V, 0.5 1.5 LOW-state (VDRVH – VLL) = 0.1 V Source resistance, (VVDD – GND) = 5 V, 0.8 1.5 HIGH-state, VVDD – VDRVL) = 0.1V RDRVL DRVL on resistance Ω Sink resistance, VDD – GND = 5 V 0.4 1.0 LOW-state, VDRVL – GND = 0.1 V TIMING CHARACTERISTICS DRVH rising, CDRVH = 3.3 nF 15 35 tDRVH DRVH transition time ns DRVH falling, CDRVH = 3.3 nF 10 35 DRVL rising, CDRVL = 3.3 nF 15 35 tDRVL DRVL transition time ns DRVL, falling, CDRVL = 3.3 nF 10 35 DRVH LOW to DRVL HIGH 5 20 tNONOVLP Driver non-overlap time ns DRVL LOW to DRVH HIGH 5 20 DCM mode: PWM rising to DRVH rising 25 tDLY(rise) PWM rising to drive output delay ns CCM mode: PWM rising to DRVL falling 25 tDLY(fall) PWM falling to drive output delay PWM falling to DRVH falling 25 ns tDLY1 3-state propagation delay to LOW PWM floating to PWM LOW 40 ns tDLY2 3-state propagation delay to HIGH PWM floating ti PWM HIGH 50 ns tTS(hold) 3-state hold-off time PWM entering tri-state from HIGH or LOW 150 ns tSKIP(pdh) SKIP LOW-to-HIGH propagation delay 15 ns tSKIP(pdl) SKIP HIGH-to-LOW propagation delay 15 ns tDRVH(min) Minimum DRVH width 80 ns Minimum DRVL width before Zero-crossing tDRVL(min) Minimum DRVL width 400 500 ns can turn OFF DRVL BOOT-STRAP SWITCH (BST) RBST BST switch on-resistance IBST = 10 mA 4 10 20 Ω IBST(leak) BST switch leakage current VBST = 34 V, VSW = 28 V 2 µA 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A |
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