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CDCVF2505IDRQ1 Datasheet(PDF) 1 Page - Texas Instruments |
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CDCVF2505IDRQ1 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 10 page 1 FEATURES 1 2 3 4 8 7 6 5 CLKIN 1Y1 1Y0 GND CLKOUT 1Y3 VDD 3.3 V 1Y2 D P (TOP VIEW) ACKAGE DESCRIPTION CDCVF2505-Q1 www.ti.com........................................................................................................................................................................................... SCAS867 – DECEMBER 2008 3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER • Qualified for Automotive Applications • Consumes Less Than 100 µA (Typically) in Power Down Mode • Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose • Internal Feedback Loop Is Used to Applications Synchronize the Outputs to the Input Clock • Spread-Spectrum Clock Compatible • 25-Ω On-Chip Series Damping Resistors • Operating Frequency: 24 MHz to 200 MHz • Integrated RC PLL Loop Filter Eliminates the Need for External Components • Low Jitter (Cycle-to-Cycle): <150 ps Over the Range 66 MHz to 200 MHz • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay) • Three-States Outputs When There Is No Input Clock • Operates From Single 3.3-V Supply • Available in 8-Pin SOIC Package The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from –40°C to 85°C. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 85°C SOIC – D Reel of 2500 CDCVF2505IDRQ1 CKV05Q (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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