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SM320C6472-HIREL Datasheet(PDF) 8 Page - Texas Instruments |
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SM320C6472-HIREL Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 264 page  SM320C6472-HiRel SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010 www.ti.com • Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. • Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. • Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following documents: • SM320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732) • SM320C64x+ DSP Cache User's Guide (literature number SPRU862) • SM320C64x+ DSP Megamodule Reference Guide (literature number SPRU871) • SM320C64x Technical Overview (literature number SPRU395) • SM320C64x to SM320C64x+ CPU Migration Guide (literature number SPRAA84) 8 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :SM320C6472-HiRel |
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