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SM320VC5409-EP Datasheet(PDF) 7 Page - Texas Instruments

No. de pieza SM320VC5409-EP
Descripción Electrónicos  FIXED-POINT DIGITAL SIGNAL PROCESSOR
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SM320VC5409-EP Datasheet(HTML) 7 Page - Texas Instruments

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SM320VC5409EP
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SGUS046 − JULY 2003
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
I/O†
INTERNAL
TERMINAL
NAME
DESCRIPTION
I/O†
PIN STATE
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal
machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the
high-impedance state when OFF is low.
CLKMD1
CLKMD2
CLKMD3
Schmitt
trigger
I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to
after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the
clock mode register is initialized to the selected mode. After reset, the clock mode can be changed
through software, but the clock mode select signals have no effect until the device is reset again.
X2/CLKIN
Schmitt
trigger
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock
input.
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should
be left unconnected. X1 does not go into the high-impedance state when OFF is low.
TOUT
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is
one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
BCLKR2
Schmitt
trigger
I/O/Z
Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input
from an external clock source for clocking data into the McBSP. When not being used as a clock,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
BDR0
BDR1
BDR2
I
Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can
be used as general-purpose I/O by setting RIOEN = 1.
BFSR0
BFSR1
BFSR2
I/O/Z
Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the
receive-data process over the BDR pin. When not being used as data-receive synchronization pins,
these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKX0
BCLKX1
BCLKX2
Schmitt
trigger
I/O/Z
Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be
configured as an input by setting the CLKXM = 0 in the PCR register. When not being used as a
clock, these pins can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
BDX0
BDX1
BDX2
O/Z
Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins
can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
BFSX0
BFSX1
BFSX2
I/O/Z
Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the
transmit-data process over BDX pin. If RS is asserted when BFSX is configured as output, then
BFSX is turned into input mode by the reset operation. When not being used as data-transmit
synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1.
These pins are placed into the high-impedance state when OFF is low.
† I = Input, O = Output, Z = High-impedance, S = Supply


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