Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

ADC1003S030 Datasheet(PDF) 9 Page - Integrated Device Technology

No. de pieza ADC1003S030
Descripción Electrónicos  Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
Download  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
Logo IDT - Integrated Device Technology

ADC1003S030 Datasheet(HTML) 9 Page - Integrated Device Technology

Back Button ADC1003S030 Datasheet HTML 5Page - Integrated Device Technology ADC1003S030 Datasheet HTML 6Page - Integrated Device Technology ADC1003S030 Datasheet HTML 7Page - Integrated Device Technology ADC1003S030 Datasheet HTML 8Page - Integrated Device Technology ADC1003S030 Datasheet HTML 9Page - Integrated Device Technology ADC1003S030 Datasheet HTML 10Page - Integrated Device Technology ADC1003S030 Datasheet HTML 11Page - Integrated Device Technology ADC1003S030 Datasheet HTML 12Page - Integrated Device Technology ADC1003S030 Datasheet HTML 13Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 19 page
background image
ADC1003S030_040_050_3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
9 of 19
Integrated Design Technology
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
[1]
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns
[2]
Analog input voltages producing code 0 up to and including code 1023:
a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(VRB) at Tamb = 25 C.
b) Voffset TOP is the difference between reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to
code 1023 at Tamb = 25 C.
[3]
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter
reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors
ROB and ROT as shown in Figure 3.
a) The current flowing into the resistor ladder is
IL
VRT VRB
ROB RL ROT
++
---------------------------------------
=
and the full-scale input range at the converter
to cover code 0 to code 1023, is
VI
RL IL
RL
ROB RL ROT
++
---------------------------------------
VRT VRB

0.848
VRT VRB

==
=
b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio
RL
ROB RL ROT
++
--------------------------------------- will
be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference VRT  VRB and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[4]
EG
V1023 V0
 V
i PP

Vi PP

-------------------------------------------------------- 100
=
[5]
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6]
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Differential phase[9]
dif
differential phase
fclk = 40 MHz;
PAL modulated ramp
-
0.4
-
deg
Timing (fclk = 40 MHz; CL = 15 pF); see Figure 4[10]
td(s)
sampling delay time
-
3
-
ns
th(o)
output hold time
4
-
-
ns
td(o)
output delay time
VCCO = 4.75 V
-
10
13
ns
VCCO = 3.15 V
-
12
15
ns
CL
load capacitance
-
-
15
pF
3-state output delay times; see Figure 5
tdZH
float to active HIGH delay
time
-
5.5
8.5
ns
tdZL
float to active LOW delay
time
-
12
15
ns
tdHZ
active HIGH to float delay
time
-
19
24
ns
tdLZ
active LOW to float delay
time
-
12
15
ns
Table 6.
Characteristics …continued
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


Número de pieza similar - ADC1003S030

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
NXP Semiconductors
ADC1003S030 NXP-ADC1003S030 Datasheet
143Kb / 20P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
Rev. 02-7 August 2008
logo
Renesas Technology Corp
ADC1003S030 RENESAS-ADC1003S030 Datasheet
485Kb / 19P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
2 July 2012
logo
NXP Semiconductors
ADC1003S030TS NXP-ADC1003S030TS Datasheet
143Kb / 20P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
Rev. 02-7 August 2008
logo
Renesas Technology Corp
ADC1003S030TS RENESAS-ADC1003S030TS Datasheet
485Kb / 19P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
2 July 2012
More results

Descripción similar - ADC1003S030

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
NXP Semiconductors
ADC1003S030 NXP-ADC1003S030 Datasheet
143Kb / 20P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
Rev. 02-7 August 2008
logo
Renesas Technology Corp
ADC1003S030 RENESAS-ADC1003S030 Datasheet
485Kb / 19P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator
2 July 2012
logo
NXP Semiconductors
ADC1004S030 NXP-ADC1004S030 Datasheet
140Kb / 19P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Rev. 03-7 August 2008
logo
Integrated Device Techn...
ADC1004S030 IDT-ADC1004S030 Datasheet
473Kb / 18P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
logo
Renesas Technology Corp
ADC1004S030 RENESAS-ADC1004S030 Datasheet
477Kb / 18P
   Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
2 July 2012
logo
NXP Semiconductors
ADC0804S030 NXP-ADC0804S030 Datasheet
140Kb / 19P
   Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Rev. 02-14 August 2008
logo
Renesas Technology Corp
ADC0804S030 RENESAS-ADC0804S030 Datasheet
487Kb / 18P
   Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
July 2012
logo
Integrated Device Techn...
ADC0804S030 IDT-ADC0804S030 Datasheet
484Kb / 18P
   Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
logo
NXP Semiconductors
ADC1206S040 NXP-ADC1206S040 Datasheet
521Kb / 32P
   Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
Rev. 02-12 August 2008
logo
Renesas Technology Corp
ADC1206S040 RENESAS-ADC1206S040 Datasheet
1Mb / 31P
   Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz
2 July 2012
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com