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ADC1113D125 Datasheet(PDF) 4 Page - Integrated Device Technology |
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ADC1113D125 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 39 page ADC1113D125 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 4 of 39 Integrated Device Technology ADC1113D125 Dual 11-bit ADC; serial JESD204A interface INBP 14 I channel B analog input VDDA 15 P analog power supply 3 V VDDA 16 P analog power supply 3 V SCLK 17 I SPI clock SDIO 18 I/O SPI data IO CS 19 I chip select AGND 20 G analog ground RESET 21 I JEDEC digital IP reset SCRAMBLER 22 I scrambler enable and disable CFG0 23 I/O see Table 28 (input) or OTRA (output)[2] CFG1 24 I/O see Table 28 (input) or OTRB (output)[2] CFG2 25 I/O see Table 28 (input) CFG3 26 I/O see Table 28 (input) VDDD 27 P digital power supply 1.8 V DGND 28 G digital ground DGND 29 G digital ground DGND 30 G digital ground VDDD 31 P digital power supply 1.8 V CMLPB 32 O channel B output CMLNB 33 O channel B complementary output VDDD 34 P digital power supply 1.8 V DGND 35 G digital ground DGND 36 G digital ground VDDD 37 P digital power supply 1.8 V CMLNA 38 O channel A complementary output CMLPA 39 O channel A output VDDD 40 P digital power supply 1.8 V DGND 41 G digital ground DGND 42 G digital ground SYNCP 43 I synchronization from FPGA SYNCN 44 I synchronization from FPGA DGND 45 G digital ground VDDD 46 P digital power supply 1.8 V SWING_0 47 I JESD204 serial buffer programmable output swing SWING_1 48 I JESD204 serial buffer programmable output swing DNC 49 O do not connect VDDA 50 P analog power supply 3 V AGND 51 G analog ground AGND 52 G analog ground Table 2. Pin description …continued Symbol Pin Type [1] Description |
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