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SN74BCT8373NT Datasheet(PDF) 6 Page - Texas Instruments

No. de pieza SN74BCT8373NT
Descripción Electrónicos  SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
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SN74BCT8373NT Datasheet(HTML) 6 Page - Texas Instruments

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SN74BCT8373
SCAN TEST DEVICE
WITH OCTAL DTYPE LATCHES
SCBS471 − JUNE 1990 − REVISED JUNE 1994
2−6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register may be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the SN74BCT8373, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.
Run-Test / Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
Upon entry to the Capture-DR state, the data register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. If the TAP controller
has not passed through the Test-Logic-Reset state since the last scan operation, TDO will enable to the level
present when it was last disabled. If the TAP controller has passed through the Test-Logic-Reset state since the
last scan operation, TDO will enable to a low level.
In the Capture-DR state, the selected data register may capture a data value as specified by the current
instruction. Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the
Capture-DR state.


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