TPIC5421L

HBRIDGE GATEPROTECTED LOGICLEVEL

POWER DMOS ARRAY

SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995

6

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

5 V

WAVEFORM

Qgd

Time

Gate Voltage

VGS

12-V

Battery

0.2

µF

50 k

Ω

0.3

µF

Current

Regulator

DUT

Same Type

as DUT

0 V

IG = 100 µA

IG Current-

Sampling Resistor

ID Current-

Sampling Resistor

VDD

TEST CIRCUIT

Qgs(th)

VDS

Qg

Figure 3. Gate-Charge Test Circuit and Waveform

VDD = 25 V

23 mH

ID

tw

tav (see Note B)

IAS

V(BR)DSX = 60 V Min

VOLTAGE AND CURRENT WAVEFORMS

0 V

0 V

0 V

ID

VDS

DUT

VDS

TEST CIRCUIT

(see Note A)

(see Note B)

Pulse Generator

50

Ω

Rgen

50

Ω

VGS

VGS

5 V

NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω .

B. Input pulse duration (tw) is increased until peak current IAS = 3 A.

Energy test level is defined as E

AS +

I

AS

V

(BR)DSX

tav

2

+ 180 mJ,

where tav = avalanche time

Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms