SN74BCT651

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3STATE OUTPUTS

SCBS054A − AUGUST 1990 − REVISED NOVEMBER 1993

Copyright

2−1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Small-Outline (DW) Packages and Standard

Plastic 300-mil DIPs (NT)

description

This SN74BCT651 consists of bus transceiver

circuits, D-type flip-flops, and control circuitry

arranged for multiplexed transmission of data

directly from the data bus or from the internal

storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.

The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.

A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four

fundamental bus-management functions that can be performed with the SN74BCT651.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the

appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and

SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when

all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.

The SN74BCT651 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1 THRU A8

B1 THRU B8

OPERATION OR FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified†

Store A, hold B

H

H

↑↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified†

Input

Hold A, store B

L

L

↑↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

stored B data to A bus

† The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,

i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

‡ When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus

setup and hold times. When select control is high, clocks must be staggered in order to load both registers.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

CLKAB

SAB

OEAB

A1

A2

A3

A4

A5

A6

A7

A8

GND

CLKBA

SBA

OEBA

B1

B2

B3

B4

B5

B6

B7

B8

DW OR NT PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.