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SN74BCT29853 Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza SN74BCT29853
Descripción Electrónicos  8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

SN74BCT29853 Datasheet(HTML) 1 Page - Texas Instruments

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DW OR NT PACKAGE
(TOP VIEW)
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OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
VCC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
SN74BCT29853
8BIT TO 9BIT PARITY BUS TRANSCEIVER
SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994
Copyright
1994, Texas Instruments Incorporated
2−1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
BiCMOS Process With TTL Inputs and
Outputs
State-of-the-Art BiCMOS Design
Significantly Reduces Standby Current
Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
Functionally Equivalent to AMD Am29853
High-Speed Bus Transceiver With Parity
Generator / Checker
Parity-Error Flag With Open-Collector
Output
Latch for Storage of the Parity-Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-erro (ERR)r flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29853 provides true logic.
The SN74BCT29853 is characterized for operation from 0
°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
OEB
OEA
CLR
LE
Ai
∑ of H’s
Bi†
∑ of H’s
A
B
PARITY
ERR‡
FUNCTION
L
H
X
X
Odd
Even
NA
NA
A
L
H
NA
A data to B bus and generate parity
H
L
X
L
NA
Odd
Even
B
NA
NA
H
L
B data to A bus and check parity
H
L
H
H
NA
X
X
NA
NA
N−1
Store error flag
X
X
L
H
X
X
X
NA
NA
H
Clear error-flag register
H
H
H
L
X
X
H
H
L
L
X
X
L Odd
H Even
X
Z
Z
Z
NC
H
H
L
Isolation§ (parity check)
L
L
X
X
Odd
Even
NA
NA
A
H
L
NA
A data to B bus and generate inverted
parity
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume the ERR output was previously high.
§ In this mode, the ERR output, when enabled, shows inverted parity of the A bus.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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