SN74HC193Q1

4BIT SYNCHRONOUS UP/DOWN COUNTER

(DUAL CLOCK WITH CLEAR)

SCLS594A − NOVEMBER 2004 − REVISED APRIL 2008

3

POST OFFICE BOX 655303

typical clear, load, and count sequence

The following sequence is illustrated below:

1.

Clear outputs to 0

2.

Load (preset) to binary 13

3.

Count up to 14, 15, carry, 0, 1, and 2

4.

Count down to 1, 0, borrow, 15, 14, and 13

Data

Inputs

Data

Outputs

LOAD

A

B

C

D

UP

CO

QA

QB

QC

QD

Clear

Count Up

013

14

0

1

2

BO

Count Down

15

14

13

DOWN

CLR

15

1

0

Preset

NOTES: A. CLR overrides LOAD, data, and count inputs.

B. When counting up, count-down input must be high; when counting down, count-up input must be high.