SN74AHC125-EP

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCLS485A – MAY 2003 – REVISED JUNE 2003

1

POST OFFICE BOX 655303

– One Assembly/Test Site, One Fabrication

Site

–55

°C to 125°C

Sources (DMS) Support

CMOS) Process

JESD 17

MIL-STD-833, Method 3015; Exceeds 150 V

Using Machine Model (C = 200 pF, R = 0)

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

description/ordering information

The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each

output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate

passes the data from the A input to its Y output.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

55

°Cto125°C

SOIC – D

Tape and reel

SN74AHC125MDREP

AHC125MEP

–55

°C to 125°C

TSSOP – PW

Tape and reel

SN74AHC125MPWREP

AH125EP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments.

D OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y