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CXB1454R Datasheet(PDF) 1 Page - Sony Corporation

No. de pieza CXB1454R
Descripción Electrónicos  VGA/SVGA/XGA 24bit Receiver
Download  17 Pages
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Fabricante Electrónico  SONY [Sony Corporation]
Página de inicio  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXB1454R Datasheet(HTML) 1 Page - Sony Corporation

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VGA/SVGA/XGA 24bit Receiver
Description
CXB1454R is the 1 chip deserializer for VGA/SVGA/
XGA 24bit color digital RGB, and meet to the Gigabit
Video Interface specification.
Features
• 1 chip receiver for serial transmission of 24-bit color
VGA/SVGA/XGA picture
• On chip cable equalizer circuit to compensate the
cable loss
• On chip PLL circuit for data and clock recovery
• On chip panel mode automatically selectable circuit
• TTL compatible I/O
• Support 1 pixel/shiftclock mode with 1 chip and 2
pixel/shiftclock mode with 2 chips
• +3.3V single power supply
• Low power consumption
• 64pin plastic LQFP package with body size 14mm
×
14mm
Structure
Bipolar silicon monolithic IC
Block Digagram & Pin out
Absolute Maximum Ratings
• Supply voltage
Vcc
4.0
V
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation
PD
1710
mW
Recommended Operating Condition
• Supply voltage
Vcc
3.3 ± 0.16
V
• Operating temperature Topr
0 to +60
°C
– 1 –
E98X24B03
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXB1454R
64 pin LQFP (Plastic)
10 11
1
Decoder
CDR
PLL
Serial
to
Parallel
Converter
12 13 14 15 16
2
3
4
5
6
7
8
9
63
64
61
62
40 39 38 37 36 35 34 33
48
41
42
43
44
45
46
47
Cable
EQ
60
59
58
57
56
55
54
53
52
51
50
49
21
30
31
32
22
23
24
25
26
27
28
29
17
18
19
20
CLKPOL
R0
R1
VEET
VccT
VEEG
VccG
R2
R3
R4
R5
VEEG
VCCG
R6
R7
VEET
CNTL
DE
SFTCLK
VEET
VccT
VEEG
VccG
HSYNC
VSYNC
B7
B6
VEEG
VccG
B5
B4
VccT
Fig. 1. Block Diagram & Pin out


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