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CXB1810FN Datasheet(PDF) 10 Page - Sony Corporation |
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CXB1810FN Datasheet(HTML) 10 Page - Sony Corporation |
10 / 17 page – 10 – CXB1810FN Low level VDAS → Deassert level VAS → Assert level VAS VDAS 3dB 3dB Hysteresis High level C1 C1 C2 15 14 12 11 100 Ω 1.5k Ω 1.5k Ω R1 R2 R1 R2 To inside the IC Fig. 5 2. Alarm block In this block, the input signal amplitude is detected and the signal interruption alarm is output when the amplitude becomes lower than the set alarm level. The alarm level setting can be adjusted by connecting an external resistor Rd between the DOWN and VCC pins. Also, this IC can set the maximum identification voltage amplitude to two levels. The maximum identification voltage amplitude is set to 50mVp-p (single ended) when the SW pin is open or high level, or to 15mVp-p (single ended) when the SW pin is low level. Figs. 15 and 16 show the relation of Rd and the alarm assert/deassert level. Setting the SW pin to low level is recommended when Rd is 510 Ω or less. Fig. 3 SW → Low 15 50 SW → High Input voltage (mVp-p, single phase) Fig. 4 In addition, the SD response deassert time is guaranteed only under the conditions noted in the AC Electrical Characteristics item, but the response becomes delayed as the input signal amplitude becomes larger. This is because the input resistor R1 shown in Fig. 1 is small at 50 Ω, so the charge accumulated in C2 is relatively large and the discharge time for this charge accounts for most of the SD response deassert time. The SD response deassert time can be shortened by using the external circuit shown in Fig. 5 or by shorting the CAP1 and CAP1B pins. However, care should be taken as the auto-offset canceler circuit does not operate in this case causing the reception sensitivity to deteriorate. Fig. 14 shows the relation between the SD response deassert time and the electrical input amplitude when using the connection shown in Fig. 5. |
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