– 5 –

CXK5T81000ATM/AYM/AM

• Read cycle (WE = “H”)

HZ1

referred to as output voltage levels.

WHZ

is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

• Write cycle

Item

Symbol

Min.

Max.

Min.

Max.

-10LLX

-12LLX

Unit

100

—

—

—

—

10

10

5

—

—

—

100

100

100

50

—

—

—

40

35

120

—

—

—

—

10

10

5

—

—

—

120

120

120

60

—

—

—

40

35

Min.

Max.

Min.

Max.

-10LLX

-12LLX

85

—

—

—

—

10

10

5

—

—

—

85

85

85

40

—

—

—

35

30

100

—

—

—

—

10

10

5

—

—

—

100

100

100

50

—

—

—

40

35

Read cycle time

Address access time

Chip enable access time (CE1)

Chip enable access time (CE2)

Output enable to output valid

Output hold from address change

Chip enable to output in low Z

(CE1, CE2)

Output enable to output in low Z (OE)

Chip disable to output in high Z

(CE1, CE2)

Output disable to output in high Z (OE)

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Item

Symbol

Min.

Max.

Min.

Max.

-10LLX

-12LLX

Unit

100

80

80

40

0

70

0

0

0

5

—

—

—

—

—

—

—

—

—

—

—

40

120

100

100

50

0

70

0

0

0

5

—

—

—

—

—

—

—

—

—

—

—

40

Min.

Max.

Min.

Max.

-10LLX

-12LLX

85

70

70

35

0

60

0

0

0

5

—

—

—

—

—

—

—

—

—

—

—

35

100

80

80

40

0

70

0

0

0

5

—

—

—

—

—

—

—

—

—

—

—

40

Write cycle time

Address valid to end of write

Chip enable to end of write

Data to write time overlap

Data hold from write time

Write pulse width

Address setup time

Write recovery time (WE)

Write recovery time (CE1, CE2)

Output active from end of write

Write to output in high Z

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns