– 8 –

CXK5V16100TM

Address

OE

Data

valid

High impedance

WE

Data out

Data in

UB, LB

CE

(

∗3)

• Write cycle (3) : UB, LB control

∗1 Write is executed when all of the CE, WE and (UB and, or LB) are at low simultaneously.

∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.

WR1

(for I/O1 to 8) is tested from either the rising edge of CE or LB, whichever comes earlier, until the end

of the write cycle.

of the write cycle.