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CXL5502M Datasheet(PDF) 4 Page - Sony Corporation |
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CXL5502M Datasheet(HTML) 4 Page - Sony Corporation |
4 / 13 page – 4 – CXL5502M/N/P Description of Function In the CXL5502M/N/P, the condition of I/O control pins (Pins 2 and 3) control the input signal clamp condition and the mode of the output signal with relation to its input signal. There are 2 modes for the I/O signal. (1) PN mode (Low level clamp/reverse phase output mode) (2) NP mode (High level clamp/positive phase output mode) I/O Control Pin (1) I/O1 (Pin 2) Control of the I/O signal condition DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling capacitor of around 1000pF is necessary. GND ............. Input signal is high level clamped and the output signal turns into an inverted signal. (2) I/O2 (Pin 3) Control of the input signal clamp condition 0V ................. Internal clamp condition 5V ................. Non internal clamp condition Center biased to approx. 2.1V by means of the IC internal resistance (several 10k Ω). Usage in this mode is limited to APL 50% signals and in this mode, the maximum input signal amplitude is 200mVp-p. Clamp level Input waveform Output waveform Clamp level |
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