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ADC08D502NOPB Datasheet(PDF) 6 Page - Texas Instruments

No. de pieza ADC08D502NOPB
Descripción Electrónicos  ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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ADC08D502NOPB Datasheet(HTML) 6 Page - Texas Instruments

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VDR
DR GND
+
-
+
-
Tdiode_P
Tdiode_N
V
VA
GND
ADC08D502
SNOSC85 – AUGUST 2012
www.ti.com
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
External bias resistor connection. Nominal value is 3.3k-Ohms
32
REXT
(±0.1%) to ground.
Temperature Diode Positive (Anode) and Negative (Cathode).
These pins may be used for die temperature measurements,
34
Tdiode_P
however no specified accuracy is implied or guaranteed. Noise
35
Tdiode_N
coupling from adjacent output data signals has been shown to
affect temperature measurements using this feature.
83 / 78
DI7
− / DQ7−
84 / 77
DI7+ / DQ7+
85 / 76
DI6
− / DQ6−
86 / 75
DI6+ / DQ6+
89 / 72
DI5
− / DQ5−
90 / 71
DI5+ / DQ5+
91 / 70
DI4
− / DQ4−
I and Q channel LVDS Data Outputs that are not delayed in the
92 / 69
DI4+ / DQ4+
output demultiplexer. Compared with the DId and DQd outputs,
93 / 68
DI3
− / DQ3−
these outputs represent the later time samples. These outputs
94 / 67
DI3+ / DQ3+
should always be terminated with a 100
Ω differential resistor.
95 / 66
DI2
− / DQ2−
96 / 65
DI2+ / DQ2+
100 / 61
DI1
− / DQ1−
101 / 60
DI1+ / DQ1+
102 / 59
DI0
− / DQ0−
103 / 58
DI0+ / DQ0+
104 / 57
DId7
− / DQd7−
105 / 56
DId7+ / DQd7+
106 / 55
DId6
− / DQd6−
107 / 54
DId6+ / DQd6+
111 / 50
DId5
− / DQd5−
112 / 49
DId5+ / DQd5+
I and Q channel LVDS Data Outputs that are delayed by one CLK
113 / 48
DId4
− / DQd4−
cycle in the output demultiplexer. Compared with the DI/DQ
114 / 47
DId4+ / DQd4+
outputs, these outputs represent the earlier time sample. These
115 / 46
DId3
− / DQd3−
outputs should always be terminated with a 100
Ω differential
116 / 45
DId3+ / DQd3+
resistor.
117 / 44
DId2
− / DQd2−
118 / 43
DId2+ / DQd2+
122 / 39
DId1
− / DQd1−
123 / 38
DId1+ / DQd1+
124 / 37
DId0
− / DQd0−
125 / 36
DId0+ / DQd0+
Out Of Range output. A differential high at these pins indicates that
79
OR+
the differential input is out of range (outside the range ±325 mV or
80
OR-
±435 mV as defined by the FSR pin).
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
82
DCLK+
signal. This signal is at 1/2 the input clock rate in SDR mode and at
81
DCLK-
1/4 the input clock rate in the DDR mode. The DCLK outputs are
not active during a calibration cycle, therefore this is not
recommended as a system clock.
2, 5, 8, 13,
16, 17, 20,
VA
Analog power supply pins. Bypass these pins to ground.
25, 28, 33,
128
6
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Product Folder Links: ADC08D502


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