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FIN424C / FIN425C • Rev. 1.0.0

3

FIN425C Deserializer Pin Descriptions

Pin Name

Description

WCLK

LVCMOS STRB Output

DP[19:0]

LVCMOS Data Output

/RES

Low-Power Mode

0 Deserializer Low Power

1 Deserializer Enabled

SLEW

Parallel Output Edge Rate Control

0 Slow Output Edge Rates

1 Fast Output Edge Rates

Test

Internal Use (Should be GND)

DS+, DS-

Serial Data Input

CKS+, CKS-

Serial Clock Input

VDDP

Power Supply for Parallel I/O and internal circuitry

VDDS

Power Supply for Serial I/O

VDDA

Power Supply for Core

GND

Ground Pins

Notes:

3.

4.

All GND and VDDP pins must be connected to ground and VDDP, respectively.

GN D PA D

M ust be G rounded

CKS+

DP[12]

DP[11]

DP[10]

VDD P

DP[9]

DP[8]

DP[7]

DP[6]

1

CKS- 2

4

V DD S

V DD A

3

DS- 5

DS+ 6

/R ES 7

V DD P 8

20

21

19

23

18

17

22

24

GN D PA D

M ust be G rounded

CKS+

DP[12]

DP[11]

DP[10]

VDD P

DP[9]

DP[8]

DP[7]

DP[6]

1

CKS- 2

4

V DD S

V DD A

3

DS- 5

DS+ 6

/R ES 7

V DD P 8

20

21

19

23

18

17

22

24

Figure 3.

FIN425CMLX MLP-32 Pinout (Top Through View)