Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AD1385 Datasheet(PDF) 7 Page - Analog Devices |
|
AD1385 Datasheet(HTML) 7 Page - Analog Devices |
7 / 20 page AD1385 REV. 0 –7– Figure 13. AD1385 Functional Block Diagram THEORY OF OPERATION The AD1385 performs conversions using a three-pass subrang- ing technique. This proven circuit concept, implemented with state of the art components, allows the ADC, track-hold, and a low noise reference to fit into a single hermetic package, simpli- fying the task of board design. The T/H and ADC portions of the AD1385 are distinct circuits with inputs and outputs avail- able on separate pins. This functional division allows greatest application flexibility. The AD1385’s major functional blocks are shown in Figure 13. The T/H uses a low noise high performance hybrid amplifier and high speed analog switches to achieve precision performance. It operates as an inverting amplifier during Track mode. Summing junction switch S1 disconnects the analog input to place the cir- cuit into Hold mode; the amplifier’s output stays constant because the dc path to its inverting input is broken. S1 also grounds the junction of R1 and R2 to minimize signal feedthrough. Pedestal is independent of the analog input level because all switching is done near ground. This ensures very low nonlinearity and distortion. A precision Reference DAC and an 8-bit flash ADC form the heart of the AD1385’s subranging design. High speed amplifiers combine the analog input and DAC output to produce the volt- ages encoded by the flash ADC during each pass. A logic array provides all necessary timing, control, and computation. The first rising clock edge after Start Convert goes high begins the conversion (provided the previous conversion is complete). The Hold Command goes high and switches the T/H into hold. The held signal from the T/H goes through S2, S3, and Error Amp 2 to the flash ADC. During this pass Error Amp 2 actually attenuates the ADC input to keep the voltage within the flash ADC’s input range. The flash ADC is strobed after a 100 ns settling period. The 8-bit result is saved in the logic array and is routed to the MSBs of the Reference DAC. Error Amp 1 amplifies the difference between the Reference DAC output and the held input signal during the second pass. S4 routes this error signal to the flash ADC, which is strobed a second time after Error Amp 1 has settled. The new 8-bit result is used to correct the previous result, increasing the accuracy of this intermediate answer to 13-bit precision. Following this the Reference DAC is updated. Both error amplifiers are active during the third pass. S2 is closed, allowing Error Amp 2 to amplify Error Amp 1’s output. S3 now brings Error Amp 2’s output to the flash ADC. The flash ADC is strobed a final time after the DAC and both error amplifiers have settled. The logic array combines the data from the third flash conversion with the earlier 13-bit word to pro- duce the final 16-bit result. The T/H is returned to track mode, and Error Amp 2 is reconnected as an attenuator 50 ns after the completion of the third flash conversion to prepare for the next conversion. The output data are placed on the data bus in two 8-bit bytes to be read by the host system. The Data Strobe output synchro- nizes the data transfer by providing a rising edge for the first byte and a falling edge for the second byte. The Hi/Lo Byte Select input allows the user to choose which data byte is pre- sented first. B1 Select sets the polarity of the MSB to provide either complementary twos complement or complementary off- set binary data. The AD1385’s internal linearity calibration capability may be used to compensate for shifts in Reference DAC linearity with time and temperature. The calibration sequence uses the AD1385’s error amplifiers and flash converter to directly mea- sure Reference DAC linearity errors. The routine calculates the Corrections required to each of the Reference DAC’s 8 MSBs and stores these in an internal memory; the memory address is determined by the Reference DAC’s codes. The RAM data con- trol a Correction DAC whose output is summed with the Refer- ence DAC’s output. Together the two DACs provide the 18-bit linearity required for accurate A/D conversions. Calibration corrects only linearity errors, and has a negligible effect on gain and offset errors. A calibration cycle requires 15 ms and may be initiated at any time (see Autozero). |
Número de pieza similar - AD1385 |
|
Descripción similar - AD1385 |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |